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Features
* Single 2.7V - 3.6V Supply * Serial Interface Architecture * Page Program Operation * * * * * * * * * * *
- Single Cycle Reprogram (Erase and Program) - 4096 Pages (528 Bytes/Page) Main Memory Optional Page and Block Erase Operations Two 528-byte SRAM Data Buffers - Allows Receiving of Data while Reprogramming of Nonvolatile Memory Internal Program and Control Timer Fast Page Program Time - 7 ms Typical 120 s Typical Page to Buffer Transfer Time Low Power Dissipation - 4 mA Active Read Current Typical - 3 A CMOS Standby Current Typical 13 MHz Max Clock Frequency Hardware Data Protection Feature Serial Peripheral Interface (SPI) Compatible - Modes 0 and 3 CMOS and TTL Compatible Inputs and Outputs Commercial and Industrial Temperature Ranges
16-megabit 2.7-volt Only Serial DataFlash(R) AT45DB161
Recommend using AT45DB161B for new designs.
Description
The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-system reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of 528 bytes each. In addition to the main memory, the AT45DB161 also contains two SRAM data buffers of 528 bytes each. The buffers allow receiving of data (continued)
Pin Configurations
Pin Name CS SCK SI SO WP RESET RDY/BUSY Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy
GND NC NC CS SCK SI SO NC NC NC NC NC NC NC
SOIC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC NC NC NC
CBGA Top View through Package
1 2 3 4 5
A
NC NC NC NC NC NC
B
NC SCK GND VCC CS RDY/BSY WP SO NC
C
NC
D
NC SI RESET NC NC NC NC
E
NC
PLCC
CS NC NC GND VCC NC NC
RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14
TSOP Top View Type 1
WP RESET RDY/BUSY NC NC NC NC NC NC
28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC
NC NC DC DC NC NC NC
14 15 16 17 18 19 20
SCK SI SO NC NC NC NC NC NC
5 6 7 8 9 10 11 12 13
4 3 2 1 32 31 30
29 28 27 26 25 24 23 22 21
Rev. 0807E-01/01
Note: PLCC package pins 16 and 17 are DON'T CONNECT
1
while a page in the main memory is being reprogrammed. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a serial interface to sequentially access its data. The simple serial interface facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size and active pin count. The device is optimized for use in many commercial and industrial applications where high density, low pin count, low voltage, and low power are essential. Typical applications for the DataFlash are digital voice storage, image storage, and data storage. The device operates at clock frequencies up
to 13 MHz with a typical active read current consumption of 4 mA. To allow for simple in-system reprogrammability, the AT45DB161 does not require high-input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB161 is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming cycles are self-timed, and no separate erase cycle is required before programming.
Block Diagram
WP FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 (528 BYTES)
BUFFER 2 (528 BYTES)
SCK CS RESET VCC GND RDY/BUSY
I/O INTERFACE
SI
SO
Memory Array
To provide optimal flexibility, the memory array of the AT45DB161 is divided into three levels of granularity comprising of sectors, blocks, and pages. The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis; however, the optional erase operations can be performed at the block or page level.
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AT45DB161
AT45DB161
Memory Architecture Diagram
SECTOR ARCHITECTURE
SECTOR 0 SECTOR 1 SECTOR 2 SECTOR 3 SECTOR 4 SECTOR 5
BLOCK ARCHITECTURE
SECTOR 0
32 Blocks (256 Pages)
BLOCK 0 BLOCK 1
PAGE ARCHITECTURE
8 Pages
PAGE 0 PAGE 1
BLOCK 30 BLOCK 31 BLOCK 32
BLOCK 0
PAGE 6 PAGE 7 PAGE 8
SECTOR 1
SECTOR 6 SECTOR 7 SECTOR 8 SECTOR 9
BLOCK 62 BLOCK 63 BLOCK 64
BLOCK 1
BLOCK 33
PAGE 9
PAGE 14 PAGE 15 PAGE 16 PAGE 17 PAGE 18
SECTOR 10 SECTOR 11 SECTOR 12 SECTOR 13
BLOCK 65 BLOCK 66
BLOCK 509 SECTOR 14 BLOCK 510 SECTOR 15 BLOCK 511
PAGE 4093 PAGE 4094 PAGE 4095
Sector = 135,168 bytes (128K + 4K)
Block = 4224 bytes (4K + 128)
Page = 528 bytes (512 + 16)
Device Operation
The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Table 1 and Table 2. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first. within the page. The 32 don't care bits which follow the 24 address bits are sent to initialize the read operation. Following the 32 don't care bits, additional pulses on SCK result in serial data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bits, and the reading of data. When the end of a page in main memory is reached during a main memory page read, the device will continue reading at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin. BUFFER READ: Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of 54H is used to read data from buffer 1, and an opcode of 56H is used to read data from buffer 2. To perform a buffer read, the eight bits of the opcode must be followed by 14 don't care bits, 10 address bits, and eight don't care bits. Since the buffer size is 528 bytes, 10 address bits (BFA9-BFA0) are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bits, the don't care bits, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A lowto-high transition on the CS pin will terminate the read operation and tri-state the SO pin. 3
Read
By specifying the appropriate opcode, data can be read from the main memory or from either one of the two data buffers. MAIN MEMORY PAGE READ: A main memory read allows the user to read data directly from any one of the 4096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, the 8-bit opcode, 52H, is followed by 24 address bits and 32 don't care bits. In the AT45DB161, the first two address bits are reserved for larger density devices (see Notes on page 10), the next 12 address bits (PA11-PA0) specify the page address, and the next 10 address bits (BA9-BA0) specify the starting byte address
MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred from the main memory to either buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and 55H for buffer 2, is followed by the two reserved bits, 12 address bits (PA11-PA0) which specify the page in main memory that is to be transferred, and 10 don't care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the SI pin. The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR ), the status register can be read to determine whether the transfer has been completed or not. MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can be compared to the data in buffer 1 or buffer 2. An 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, is followed by 24 address bits consisting of the two reserved bits, 12 address bits (PA11-PA0) which specify the page in the main memory that is to be compared to the buffer, and 10 don't care bits. The loading of the opcode and the address bits is the same as described previously. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don't care bits from the SI pin. On the low-to-high transition of the CS pin, the 528 bytes in the selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. During this time (tXFR), the status register will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare.
occurs on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register will indicate that the part is busy. BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A previously erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, is followed by the two reserved bits, 12 address bits (PA11-PA0) that specify the page in the main memory to be written, and 10 additional don't care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously erased. The programming of the page is internally self-timed and should take place in a maximum time of tP. During this time, the status register will indicate that the part is busy. PAGE ERASE: The optional Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized at a later time. To perform a Page Erase, an opcode of 81H must be loaded into the device, followed by two reserved bits, 12 address bits (PA11-PA0), and 10 don't care bits. The 12 address bits are used to specify which page of the memory array is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected page to 1s. The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the status register will indicate that the part is busy. BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized to reduce programming times when writing large amounts of data to the device. To perform a Block Erase, an opcode of 50H must be loaded into the device, followed by two reserved bits, nine address bits (PA11-PA3), and 13 don't care bits. The nine address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages to 1s. The erase operation is internally self-timed and should take place in a maximum time of tBE. During this time, the status register will indicate that the part is busy.
Program
BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2. To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, is followed by 14 don't care bits and 10 address bits (BFA9BFA0). The 10 address bits specify the first byte in the buffer to be written. The data is entered following the address bits. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-tohigh transition is detected on the CS pin. BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. An 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, is followed by the two reserved bits, 12 address bits (PA11-PA0) that specify the page in the main memory to be written, and 10 additional don't care bits. When a low-to-high transition
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AT45DB161
AT45DB161
Block Erase Addressing
PA11 0 0 0 0 * * * 1 1 1 1 PA10 0 0 0 0 * * * 1 1 1 1 PA9 0 0 0 0 * * * 1 1 1 1 PA8 0 0 0 0 * * * 1 1 1 1 PA7 0 0 0 0 * * * 1 1 1 1 PA6 0 0 0 0 * * * 1 1 1 1 PA5 0 0 0 0 * * * 1 1 1 1 PA4 0 0 1 1 * * * 0 0 1 1 PA3 0 1 0 1 * * * 0 1 0 1 PA2 X X X X * * * X X X X PA1 X X X X * * * X X X X PA0 X X X X * * * X X X X Block 0 1 2 3 * * * 508 509 510 511
MAIN MEMORY PAGE PROGRAM: This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then programmed into a specified page in the main memory. An 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, is followed by the two reserved bits and 22 address bits. The 12 most significant address bits (PA11-PA0) select the page in the main memory where data is to be written, and the next 10 address bits (BFA9-BFA0) select the first byte in the buffer to be written. After all address bits are shifted in, the part will take data from the SI pin and store it in one of the data buffers. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum of time tEP. During this time, the status register will indicate that the part is busy. AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. An 8-bit opcode, 58H for buffer 1 or 59H for buffer 2, is followed by the two reserved bits, 12 address bits (PA11-PA0) that specify the page in main memory to be rewritten, and 10 additional don't care bits. When a low-to-high transition occurs on the CS pin, the part will first transfer data from the page in main memory to
a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of tEP. During this time, the status register will indicate that the part is busy. If a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in Figure 1 on page 17 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 2 on page 18 is recommended. STATUS REGISTER: The status register can be used to determine the device's ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or the device density. To read the status register, an opcode of 57H must be loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the next eight clock cycles. The five most significant bits of the status register will contain device information, while the remaining three least significant bits are reserved for future use and will have undefined values. After bit 0 of the status register has been shifted out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled) starting again with bit 7. The data in the status register is constantly updated, so each repeating sequence will output new data. Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. The user can continuously poll bit 7 of the status register by stopping SCK once bit 7 has been output. The status of bit 7 will continue to be output on the SO pin, and once the device is no longer busy, the state of SO will change from 0 to 1. There are eight operations which can 5
cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Compare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. The device density is indicated using bits 5, 4, and 3 of the status register. For the AT45DB161, the three bits are 1, 0, and 1. The decimal value of these three binary bits does not equate to the device density; the three bits represent a combinational code relating to differing densities of Serial DataFlash devices, allowing a total of eight different density configurations.
This gives the serial DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 ("Using Atmel's Serial DataFlash") for more details. HARDWARE PAGE WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive the protect pin high and then use the program commands previously mentioned. The WP pin is internally pulled high; therefore, connection of the WP pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the WP pin be driven high externally whenever possible. RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, connection of the RESET pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the RESET pin be driven high externally whenever possible. READY/BUSY: This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming operations, compare operations, and during page-tobuffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed.
Read/Program Mode Summary
The modes listed above can be separated into two groups -- modes which make use of the Flash memory array (Group A) and modes which do not make use of the flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Main Memory Page to Buffer 1 (or 2) Transfer 3. Main Memory Page to Buffer 1 (or 2) Compare 4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase 5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase 6. Page Erase 7. Block Erase 8. Main Memory Page Program 9. Auto Page Rewrite Group B modes consist of: 1. Buffer 1 (or 2) Read 2. Buffer 1 (or 2) Write 3. Status Register Read If a Group A mode is in progress (not fully completed) then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started.
Power-on/Reset State
When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state.
Status Register Format
Bit 7 RDY/BUSY Bit 6 COMP Bit 5 1 Bit 4 0 Bit 3 1 Bit 2 X Bit 1 X Bit 0 X
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AT45DB161
AT45DB161
Absolute Maximum Ratings*
Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC and AC Operating Range
AT45DB161 Operating Temperature (Case)
(1)
Com. Ind.
0C to 70C -40C to 85C
VCC Power Supply 2.7V to 3.6V Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started.
7
DC Characteristics
Symbol ISB ICC1 ICC2 ILI ILO VIL VIH VOL VOH Parameter Standby Current Active Current, Read Operation Active Current, Program/Erase Operation Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 2.7V IOH = -100 A VCC - 0.2V 2.0 0.4 Condition CS, RESET, WP = VIH, all inputs at CMOS levels f = 13 MHz; IOUT = 0 mA; VCC = 3.6V VCC = 3.6V VIN = CMOS levels VI/O = CMOS levels Min Typ 3 4 15 Max 10 10 35 1 1 0.6 Units A mA mA A A V V V V
AC Characteristics
Symbol fSCK tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tEP tP tPE tBE tRST tREC Parameter SCK Frequency SCK High Time SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Erase and Programming Time Page Programming Time Page Erase Time Block Erase Time RESET Pulse Width RESET Recovery Time 10 1 250 10 7 6 7 10 20 0 25 30 350 20 15 10 15 35 35 250 250 250 200 Min Typ Max 13 Units MHz ns ns ns ns ns ns ns ns ns ns ns s ms ms ms ms s s
Input Test Waveforms and Measurement Levels
AC DRIVING LEVELS 2.4V 2.0 0.8 0.45V AC MEASUREMENT LEVEL
Output Test Load
DEVICE UNDER TEST 30 pF
tR, tF < 5 ns (10% to 90%)
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AT45DB161
AT45DB161
AC Waveforms
Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low when CS makes a highto-low transition, and Waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal. Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows timing that is compatible with SPI Mode 3
Waveform 1 - Inactive Clock Polarity Low
tCS CS tCSS SCK tV SO HIGH IMPEDANCE tSU SI VALID IN tH tHO VALID OUT tDIS HIGH IMPEDANCE tWH tWL tCSH
Waveform 2 - Inactive Clock Polarity High
tCS CS tCSS SCK tV SO HIGH Z tSU SI VALID IN tHO VALID OUT tH tDIS HIGH IMPEDANCE tWL tWH tCSH
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Reset Timing (Inactive Clock Polarity Low Shown)
CS
tREC tCSS
SCK
tRST
RESET
HIGH IMPEDANCE HIGH IMPEDANCE
SO SI
Command Sequence for Read/Write Operations (except Status Register Read)
SI CMD 8 bits 8 bits 8 bits
MSB
r r X X XXXX Reserved for larger densities
XXXX XXXX
XXXX XXXX
LSB
Page Address (PA11-PA0)
Byte/Buffer Address (BA9-BA0/BFA9-BFA0)
Notes:
1. "r" designates bits reserved for larger densities. 2. It is recommended that "r" be a logical "0" for densities of 16M bits or smaller. 3. For densities larger than 16M bits, the "r" bits become the most significant Page Address bit for the appropriate density.
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AT45DB161
AT45DB161
Write Operations
The following block diagram and waveforms illustrate the various write sequences available.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 1 TO MAIN MEMORY PAGE PROGRAM MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 BUFFER 2 TO MAIN MEMORY PAGE PROGRAM
BUFFER 1 (528 BYTES)
BUFFER 1 WRITE MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1
BUFFER 2 (528 BYTES)
BUFFER 2 WRITE
I/O INTERFACE
SI
Main Memory Page Program through Buffers
* Completes writing into selected buffer * Starts self-timed erase/program operation
CS SI
CMD r r , PA11-6
PA5-0, BFA9-8
BFA7-0
n
n+1
Last Byte
Buffer Write
* Completes writing into selected buffer
CS SI
CMD X
X***X, BFA9-8 BFA7-0
n
n+1
Last Byte
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
Starts self-timed erase/program operation
CS SI
CMD r r , PA11-6 PA5-0, XX X
Each transition represents 8 bits and 8 clock cycles
n = 1st byte written n+1 = 2nd byte written
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Read Operations
The following block diagram and waveforms illustrate the various read sequences available.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
MAIN MEMORY PAGE TO BUFFER 1 MAIN MEMORY PAGE TO BUFFER 2
BUFFER 1 (528 BYTES)
BUFFER 1 READ
BUFFER 2 (528 BYTES)
MAIN MEMORY PAGE READ BUFFER 2 READ
I/O INTERFACE
SO
Main Memory Page Read
CS SI SO
CMD r r , PA11-6 PA5-0, BA9-8 BA7-0 X X X X n n+1
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Starts reading page data into buffer
CS SI SO
CMD r r , PA11-6 PA5-0, XX X
Buffer Read
CS SI SO
CMD X
X***X, BFA9-8 BFA7-0
X n n+1
Each transition represents 8 bits and 8 clock cycles
n = 1st byte read n+1 = 2nd byte read
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AT45DB161
AT45DB161
Detailed Bit-level Read Timing - Inactive Clock Polarity Low
Main Memory Page Read
CS
SCK tSU
1
2
3
4
5
60
61
62
63
64
65
66
67
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH-IMPEDANCE
DATA OUT
D7 MSB D6 D5
Buffer Read
CS
SCK tSU
1
2
3
4
5
36
37
38
39
40
41
42
43
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH-IMPEDANCE
DATA OUT
D7 MSB D6 D5
Status Register Read
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
16
17
COMMAND OPCODE SI
0 1 0 1 0 1 1 1
tV SO HIGH-IMPEDANCE
D7 MSB
STATUS REGISTER OUTPUT
D6 D5 D1 D0 LSB D7 MSB
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Detailed Bit-level Read Timing - Inactive Clock Polarity High
Main Memory Page Read
CS
SCK tSU
1
2
3
4
5
61
62
63
64
65
66
67
68
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH-IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Buffer Read
CS
SCK tSU
1
2
3
4
5
37
38
39
40
41
42
43
44
COMMAND OPCODE SI
0 1 0 1 0 X X X X X
tV SO HIGH-IMPEDANCE
D7 MSB
DATA OUT
D6 D5 D4
Status Register Read
CS
SCK tSU
1
2
3
4
5
6
7
8
9
10
11
12
17
18
COMMAND OPCODE SI
0 1 0 1 0 1 1 1
tV SO HIGH-IMPEDANCE
D7 MSB
STATUS REGISTER OUTPUT
D6 D5 D4 D0 LSB D7 MSB D6
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AT45DB161
AT45DB161
Table 1.
Main Memory Page Read 52H 0 1 0 1 0 0 1 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 X X X X X X X X * * * X (64th bit) Buffer 1 Read 54H 0 1 0 1 0 1 0 0 X X X X X X X X X X X X X X BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 X X X X X X X X Buffer 2 Read 56H 0 1 0 1 0 1 1 0 X X X X X X X X X X X X X X BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 X X X X X X X X Main Memory Page to Buffer 1 Transfer 53H 0 1 0 1 0 0 1 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X Main Memory Page to Buffer 2 Transfer Opcode 55H 0 1 0 1 0 1 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X Main Memory Page to Buffer 1 Compare 60H 0 1 1 0 0 0 0 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X Main Memory Page to Buffer 2 Compare 61H 0 1 1 0 0 0 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X Buffer 1 Write 84H 1 0 0 0 0 1 0 0 X X X X X X X X X X X X X X BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 Buffer 2 Write 87H 1 0 0 0 0 1 1 1 X X X X X X X X X X X X X X BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
X (Don't Care) r (reserved bits)
15
Table 2.
Buffer 1 to Main Memory Page Program with Built-in Erase Buffer 2 to Main Memory Page Program with Built-in Erase Buffer 1 to Main Memory Page Program without Built-in Erase
Buffer 2 to Main Memory Page Program without Built-in Erase
Page Erase Opcode
Block Erase
Main Memory Page Program through Buffer 1
Main Memory Page Program through Buffer 2
Auto Page Rewrite through Buffer 1
Auto Page Rewrite through Buffer 2
Status Register
83H 1 0 0 0 0 0 1 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
86H 1 0 0 0 0 1 1 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
88H 1 0 0 0 1 0 0 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
89H 1 0 0 0 1 0 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
81H 1 0 0 0 0 0 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
50H 0 1 0 1 0 0 0 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 X X X X X X X X X X X X X
82H 1 0 0 0 0 0 1 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
85H 1 0 0 0 0 1 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0
58H 0 1 0 1 1 0 0 0 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
59H 0 1 0 1 1 0 0 1 r r PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 X X X X X X X X X X
57H 0 1 0 1 0 1 1 1
X (Don't Care) r (reserved bits)
16
AT45DB161
AT45DB161
Figure 1. Algorithm for Sequentially Programming or Reprogramming an Entire Sector
START provide address and data
BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM (82H, 85H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H, 86H)
END
Notes:
1. This type of algorithm is used for applications in which an entire sector is programmed sequentially, filling the sector pageby-page. 2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire sector.
17
Figure 2. Algorithm for Randomly Modifying Data
START provide address of page to modify MAIN MEMORY PAGE to BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array
BUFFER WRITE (84H, 87H)
MAIN MEMORY PAGE PROGRAM (82H, 85H) BUFFER to MAIN MEMORY PAGE PROGRAM (83H, 86H)
Auto Page Rewrite (58H, 59H)
(2)
INCREMENT PAGE (2) ADDRESS POINTER
END
Notes:
1. To preserve data integrity, each page of a DataFlash sector (256 pages per sector) must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations within that sector. 2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer. 3. Other algorithms can be used to rewrite portions of the Flash array. Low power applications may choose to wait until 10,000 cumulative page erase/program operations have accumulated before rewriting all 256 pages of the sector. See application note AN-4 ("Using Atmel's Serial DataFlash") for more details.
Sector Addressing
PA11 0 0 0 PA10 0 0 0 PA9 0 0 1 PA8 0 1 0 Sector 0 1 2
* * *
* * *
* * *
* * *
* * *
1 1 1
1 1 1
0 1 1
1 0 1
13 14 15
18
AT45DB161
AT45DB161
Ordering Information
fSCK (MHz) 13 ICC (mA) Active 10 Standby 0.01 Ordering Code AT45DB161-JC AT45DB161-RC AT45DB161-TC AT45DB161-CC AT45DB161-JI AT45DB161-RI AT45DB161-TI AT45DB161-CI Package 32J 28R 28T 24C2 32J 28R 28T 24C2 Operation Range Commercial (0C to 70C)
13
10
0.01
Industrial (-40C to 85C)
Package Type 32J 28R 28T 24C2 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) 24-ball, 5 x 5 Array Plastic Chip-Scale Ball Grid Array (CBGA)
19
Packaging Information
24C2, 24-ball (5 x 5 Array), 1.0 mm Pitch, 7 x 9.5 mm Plastic Chip-scale Ball Grid Array (CBGA) Dimensions in Millimeters and (Inches)*
7.2 (0.283) 6.8 (0.268)
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45
PIN NO. 1 IDENTIFY
.025(.635) X 30 - 45 .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05)
9.7 (0.381) 9.3 (0.366)
.032(.813) .026(.660)
.553(14.0) .547(13.9) .595(15.1) .585(14.9)
0.30 (0.012) 1.40 (0.055) MAX
.050(1.27) TYP
1.62 (0.064) 1.36 (0.054)
5
4.0 (0.157)
4 3 2 1
2.87 (0.113) 2.61 (0.103)
.300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS
A B C D E
4.0 (0.157)
.022(.559) X 45 MAX (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3)
0.46 (0.018) DIA BALL TYP 1.00 (0,039) BSC NON-ACCUMULATIVE
*Controlling dimension: millimeters 28R, 28-lead, 0.330" Wide, Plastic Gull Wing Small Outline (SOIC) Dimensions in Inches and (Millimeters) 28T, 28-lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)*
INDEX MARK AREA 11.9 (0.469) 11.7 (0.461) 13.7 (0.539) 13.1 (0.516)
0.55 (0.022) BSC 7.15 (0.281) REF 8.10 (0.319) 7.90 (0.311)
0.27 (0.011) 0.18 (0.007)
1.25 (0.049) 1.05 (0.041)
0.20 (0.008) 0.10 (0.004) 0 REF 5 0.20 (0.008) 0.15 (0.006)
0.70 (0.028) 0.30 (0.012)
*Controlling dimension: millimeters
20
AT45DB161
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0807E-01/01//xM

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